1. Field of the invention
The present invention relates to an operational amplifier, and more specifically to an operational amplifier having a wide input/output range.
2. Description of related art
Prior art operational amplifiers include an operational amplifier having a wide input/output range and are generally capable of driving a large load. One example of this type operational amplifier was proposed by the inventor in U.S. Pat. No. 5,670,910, the content of which is incorporated by reference in its entirety into this application.
Now, the example of this type of operational amplifier will be described with reference to a circuit diagram as shown in FIG. 8.
As shown in FIG. 8, this type of operational amplifier can be generally divided into an input stage 10 connected to signal input terminals 1 and 2 for receiving and amplifying a signal between the signal input terminals 1 and 2 in a differential manner, and an output stage 20 for driving an output signal terminal 3 for outputting an amplified signal.
The input stage 10 includes:
a differential transistor pair composed of a pair of N-channel field effect transistors M1 and M2 having their sources connected to each other and their gates connected to the signal input terminals 2 and 1, respectively; PA1 a first constant current source I1 connected between the common-connected sources of the N-channel field effect transistors M1 and M2 and a low potential power supply line 4; PA1 a P-channel field effect transistor M3 having a gate and a drain connected in common to a drain of the N-channel field effect transistor M1 and a source connected to a high potential power supply line 5; PA1 a P-channel field effect transistor M4 having a source connected to the high potential power supply line 5, a gate connected to the gate and the drain of the P-channel field effect transistor M3, and a drain connected to a drain of the N-channel field effect transistor M2; PA1 another differential transistor pair composed of a pair of P-channel field effect transistors M5 and M6 having their sources connected to each other and their gates connected to the signal input terminals 1 and 2, respectively; PA1 a second constant current source I2 connected between the common-connected sources of the P-channel field effect transistors M5 and M6 and the high potential power supply line 5; PA1 an N-channel field effect transistor M7 having a gate and a drain connected to a drain of the P-channel field effect transistor M5 and a source connected to the low potential power supply line 4; PA1 an N-channel field effect transistor M8 having a gate and a drain connected to a drain of the P-channel field effect transistor M6 and a source connected to the low potential power supply line 4; PA1 an N-channel field effect transistor M9 connected to the N-channel field effect transistor M7 to form a current mirror circuit and having a drain connected to the drain of the P-channel field effect transistor M3; and PA1 an N-channel field effect transistor M10 connected to the N-channel field effect transistor M8 to form a current mirror circuit and having a drain connected to the drain of the P-channel field effect transistor M4. PA1 a P-channel field effect transistor M11 and a P-channel field effect transistor M13 having their sources connected to the high potential power supply line 5, and their gates connected in common to the drains of the P-channel field effect transistor M4, the N-channel field effect transistor M2 and the N-channel field effect transistor M10; PA1 a third constant current source I3 connected between a drain of the P-channel field effect transistor M11 and the low potential power supply line 4; PA1 a P-channel field effect transistor M12 having a source connected to the high potential power supply line 5, a gate connected to a connection node between the drain of the P-channel field effect transistor M11 and the third constant current source I3; PA1 a fourth constant current source I4 connected between a drain of the P-channel field effect transistor M12 and the low potential power supply line 4; and PA1 an N-channel field effect transistor M14 having a source connected to the low potential power supply line 4 and a gate connected to a connection node between the drain of the P-channel field effect transistor M12 and the fourth constant current source I4, PA1 a drain of the P-channel field effect transistor M13 and a drain of the N-channel field effect transistor M14 being connected to the output signal terminal 3. PA1 an input stage having a differential transistor pair composed of a pair of transistors connected between a constant current source and two output nodes and having control electrodes connected to two signal input terminals, respectively, so that a signal applied between the two signal input terminals is amplified in a differential manner, and an output signal is obtained from a selected output node of the two output nodes; PA1 an output stage having two output transistors of different conductivity types, connected in series between two power supply terminals, a connection node between the two output transistors being connected to an output signal terminal, and a level shift circuit receiving the output signal of the input stage for generating a level-shifted signal of the output signal of the input stage, the output signal of the input stage and the level-shifted signal being applied to control electrodes of the two output transistors, respectively, so that the two output transistors drives the output signal terminal in a push-pull manner, PA1 a capacitance between the selected output node of the input stage and the output signal terminal, PA1 the input stage including a first bias current supplementing means connected in parallel to the constant current source, for selectively supplying an additional bias current to the differential transistor pair in accordance with one of the output signal of the input stage and the level-shifted signal. PA1 wherein a second bias current supplementing means is connected in parallel to the second constant current source, for selectively supplying an additional bias current to the second differential transistor pair in accordance with one of the output signal of the input stage and the level-shifted signal, independently of the first mentioned additional bias current supplied to the first mentioned differential transistor pair.
On the other hand, the output stage 20 includes:
As seen from the above, in the above construction, the drain of the N-channel field effect transistor M2 constitutes an output of the input stage 10.
Next, an operation of the above mentioned prior art operational amplifier will be described.
This prior art operational amplifier includes the input stage having a wide input range, composed of the differential transistor pair formed of the N-channel field effect transistors M1 and M2 and the differential transistor pair formed of the N-channel field effect transistors M5 and M6, these differential transistor pairs being connected in parallel, and the drain of the N-channel field effect transistor M2 being connected to the output stage as the output of the input stage. In the output stage, the output of the input stage is connected to the gate of the P-channel field effect transistor M13 so as to change a gate voltage in accordance with a difference between signal voltages applied to the signal input terminals 1 and 2, and at the same time, the output of the input stage is level-shifted through the P-channel field effect transistor M11 and the P-channel field effect transistor M12, so that this level-shifted signal is applied to the gate of the N-channel field effect transistor M14 so as to simultaneously change the gate voltage of the N-channel field effect transistor M14. In accordance with the respective gate voltage changes of these field effect transistors M13 and M14, the potential of the output signal terminal 3 quickly elevates or drops.
For example, when the voltage applied to the signal input terminal is higher than that applied to the signal input terminal 2, the output of the input stage 10 supplied from the drain of the field effect transistor M2 of the differential transistor pair, becomes low, and therefore, the gate voltage of the P-channel field effect transistors M11 and M13 of the output stage 20 becomes low. At this time, a current flowing from the high potential power supply line 5 through the P-channel field effect transistor M13 to the output signal terminal 3 becomes very large. At the same time, the potential of the connection node between the drain of the P-channel field effect transistor M11 and the third constant current source I3, namely, the gate potential of the P-channel field effect transistor M12 becomes high. As a result, the potential of the connection node between the drain of the P-channel field effect transistor M12 and the fourth constant current source I4, namely, the level shifted signal applied to the gate of the N-channel field effect transistor M14 becomes low. Accordingly, a current flowing from the output signal terminal 3 through the N-channel field effect transistor M14 to the low potential power supply line 4, becomes very small.
Thus, since the current flowing through the P-channel field effect transistor M13 is large and the current flowing through the N-channel field effect transistor M14 is in a cutoff condition, the potential of the signal output terminal 3 can be caused to quickly elevate.
On the other hand, when the voltage applied to the signal input terminal 1 is lower than that applied to the signal input terminal 2, the output of the input stage 10 supplied from the drain of the field effect transistor M2 of the differential transistor pair, becomes high, and therefore, the gate voltage of the P-channel field effect transistors M11 and M13 of the output stage 20 becomes high. At this time, the current flowing from the high potential power supply line 5 through the P-channel field effect transistor M13 to the output signal terminal 3 becomes very small. At the same time, the potential of the connection node between the drain of the P-channel field effect transistor M11 and the third constant current source I3, namely, the gate potential of the P-channel field effect transistor M12 becomes low. As a result, the potential of the connection node between the drain of the P-channel field effect transistor M12 and the fourth constant current source I4, namely, the level shifted signal applied to the gate of the N-channel field effect transistor M14 becomes high. Accordingly, the current flowing from the output signal terminal 3 through the N-channel field effect transistor M14 to the low potential power supply line 4, becomes very large.
Thus, since the current flowing through the N-channel field effect transistor M14 is large and the current flowing through the P-channel field effect transistor M13 is in a cutoff condition, the potential of the signal output terminal 3 can be caused to quickly drop.
In this prior art operational amplifier, the potential of the signal output terminal 3 can change in a wide output range from a potential which is lower than the potential of the high potential power supply line 5 by the drain-source voltage of the P-channel field effect transistor M13, to a potential which is higher than the potential of the low potential power supply line 4 by the drain-source voltage of the N-channel field effect transistor M14.
In a balanced condition, an idling current flowing through the P-channel field effect transistor M13 and the N-channel field effect transistor M14, is determined by a size ratio between the P-channel field effect transistor M11 and the P-channel field effect transistor M13 and a current flowing through the constant current source I3. For example, assuming that the current flowing through the constant current source I3 is I (.mu.A) and the size ratio of the P-channel field effect transistor M11 to the P-channel field effect transistor M13 is 1:2, the idling current flowing through the P-channel field effect transistor M13 and the N-channel field effect transistor M14 becomes 2I(.mu.A).
As mentioned above, the circuit shown in FIG. 8 realizes an operation amplifier having a wide input range and a wide output range and capable of quickening the elevation and the drop of the potential of the signal output terminal 3.
Here, a slew rate dV0/dt of the rising voltage and the falling voltage of this operational amplifier is one parameter indicating the performance of the operational amplifier, and is roughly expressed by an equation dV0/dt=K.multidot.Ii/C (where "K" is a proportional constant). If this value is large, the potential of the output signal terminal can be quickly elevated or dropped. Here, the variable "Ii" is a bias current supplied from the constant current source to the differential transistor pair of the input stage. The variable "C" is a phase compensating capacitance for preventing deterioration of the high frequency characteristics of the operational amplifier, which is preferably connected between the gate and the drain of the P-channel field effect transistor M13 as shown in FIG. 8.
As seen from the above equation, the slew rate of the operational amplifier greatly depends upon the bias current caused to flow in the input stage. Therefore, in order to enlarge the slew rate so as to quicken the rising and the falling of the output signal, it is required in the existing circuit construction to enlarge the bias current supplied to the differential transistor pair in the input stage, namely, respective values of the first constant current source I1 and the second constant current source I2 in the circuit shown in FIG. 8. In this case, however, the whole consumed current of the operational amplifier inevitably increases.